Implementation of Self Addressing RAM

Authors : Kiran P V; Naveen Kumar Kanavi; Gita Reshmi; Veena A

Volume/Issue : Volume 7 - 2022, Issue 2 - February

Google Scholar :

Scribd :


This paper aims to implement a RAM which can address itself to load the data into its memory. Using Xilinx 14.1 ISE for simulation and synthesis the RAM of size 16 x 32 is implemented with consecutive addresses generated automatically by the additional circuit in the design.

Keywords : RAM, BRAM, Single Port BRAM, Dual Port BRAM.


Paper Submission Last Date
30 - April - 2024

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Video Explanation for Published paper

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.