XOR Based Carry Select Adder for Area and Delay Minimization Using GDI Technology

Authors : Ramyabanu Bobba; Pooja Illa

Volume/Issue : Volume 5 - 2020, Issue 6 - June

Google Scholar : http://bitly.ws/9nMw

Scribd : https://bit.ly/330EpzK

DOI : 10.38124/IJISRT20JUN1117

Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and complexity minimization. The proposed 16-bit carry select adder provides better results compared to the conventional 16-bit carry select adder with Area and delay.

Keywords : Optimized multiplexer-based adder, carry select adder, GDI technology.


Paper Submission Last Date
30 - June - 2023

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Video Explanation for Published paper

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.