Authors :
D. Anupriya
Volume/Issue :
Volume 7 - 2022, Issue 12 - December
Google Scholar :
https://bit.ly/3IIfn9N
Scribd :
https://bit.ly/3PECdUG
DOI :
https://doi.org/10.5281/zenodo.7460478
Abstract :
Since integrated circuit designs continuously
expanding, which makes the verification process more
difficult and time-consuming, effective verification of such
circuit designs is essential. As a result, a strong testbench
structure is required, one that includes major generic
verification components that are highly reusable and are
simple to adapt to new designs. The UVM hierarchy is one
such design capable of realizing testbench architectures
with coverage-driven verification environments with CRT
(constrained Random Test). According to the verification
plan devised following a thorough review of the SPI
protocol requirements, the current effort is appropriately
concentrated on SPI One Master and Multi Slave protocol
verification using UVM. The UVM Testbench
concentrates on generating random vectors that are sent to
the SPI module or the DUT (Design Under Test). This
method aids in verifying the functionality of SPI by
making comparisons with the captured response received
via scoreboard. By using acceptable or appropriate test
cases, Testbench also validates the functionality and
distinguishing characteristics of SPI, and at the conclusion
of the test, it delivers a cumulative coverage report of the
design.
Keywords :
UVM, System Verilog, SPI Protocol, Questsim, and EDA-playground mentor.
Since integrated circuit designs continuously
expanding, which makes the verification process more
difficult and time-consuming, effective verification of such
circuit designs is essential. As a result, a strong testbench
structure is required, one that includes major generic
verification components that are highly reusable and are
simple to adapt to new designs. The UVM hierarchy is one
such design capable of realizing testbench architectures
with coverage-driven verification environments with CRT
(constrained Random Test). According to the verification
plan devised following a thorough review of the SPI
protocol requirements, the current effort is appropriately
concentrated on SPI One Master and Multi Slave protocol
verification using UVM. The UVM Testbench
concentrates on generating random vectors that are sent to
the SPI module or the DUT (Design Under Test). This
method aids in verifying the functionality of SPI by
making comparisons with the captured response received
via scoreboard. By using acceptable or appropriate test
cases, Testbench also validates the functionality and
distinguishing characteristics of SPI, and at the conclusion
of the test, it delivers a cumulative coverage report of the
design.
Keywords :
UVM, System Verilog, SPI Protocol, Questsim, and EDA-playground mentor.