Reduction Techniques for Power and Delay on Full Adder by XOR Gate Logics Using Microwind EDA Tool


Authors : S.I. Padma, ME; S. Archana Devi; R.Jenifer; V. Pramma Sathya

Volume/Issue : Volume 6 - 2021, Issue 3 - March

Google Scholar : http://bitly.ws/9nMw

Scribd : https://bit.ly/3263NCp

Full adder circuit is central to most digital circuits that slaves a significant port in the design of particular integrated circuits. Power dissipation and delay are the momentous parameter of the circuits. Therefore reducing power consumption and delay in full adder and XOR gate using various logics like, Transmission gate logic(TGL),Pass Transistor logic(PTL) and static complementary metal oxide semiconductor (CMOS)logic, Dual rail Domino Logic and Domino Logic , Double Pass Transistor (DPL).The circuits are designed and implemented, simulated using Microwind EDA tool. Using the comparative power and delay analysis, the designer requiredan sufficient adder design can be select based on the parametercriteria

Keywords : Transmission gate logic, Pass, Transistor Logic , Double Pass Transistor Logic DPL, Domino Logic, Dual rail domino logic , Microwind EDA

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