In the previous paper, present an application of a 4-bit SISO shift register by making use of a combination of ADOC schema & RTPG. They have also suggested Activity-Driven Fine-Grained CG & RTPG integration. Initially, an ADOC (Activity Driven Optimized Clock Gating Schema) is presented for enhancing the conventional CG based over XOR logic gate. It selects a sub group of flip flops that are gated over a selective basis. Further we incorporate RTPG that is implemented to each of the flip flop. The ADOC schema produces clock enable signals that are applied like sleep signal to each of the PG cell. This assessment is conducted by making use of Tanner EDA by implementing 250 nm methodology. The outcomes of simulation express that SISO shift registers along the RTPG & ADOC technology is 72.03% more efficient than the SISO shift register. In this paper, the XOR logic gate is replaced by NAND logic gate & the GDI methodology is also applied for minimization of consumption of power in the circuitry. The OR gate is replaced by OR gate based over GDI technique. This GDI methodology has the ability of minimizing the consumption of power in the circuitry.
Keywords : Power Gating; Clock Gating; Activity-Driven Optimized Clock-gating; Run Time Power Gating; Serial Input Serial Output Shift Register.