Low Power Consumption Based Johnson Counter by Transistor Gating Technique

Authors : Ajay Kumar.

Volume/Issue : Volume 4 - 2019, Issue 3 - March

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://bit.ly/2WNRtpy

Johnson counter is an important counter which is mainly used to deliver data of particular concept in a continuous loop. This method is essential for varying logic designs. Normally data that follows this pattern is placed inside a certain place that follows the same design and a perfect logic function is constructed. The presence of the counter system is an essential part of these logic designs since they provide a wide range of sequences. In the Present time , Every Digital circuit is going to short in Area. In this case , Power Consumption is a crucial Point. Johnson Counter is using in many Digital Circuits. In this paper, we are working for the Power Consumption of the 4 Bit Johnson Counter. For Reduce the Power Consumption , using Transistor Gating Technique. It will reduce the Power consumption of the NAND gate , D Flip Flop and PIPO Circuit. For Design the circuit, working at 130 nm Channel length file.

Keywords : CMOS, Counter, Flip-Flop, Johnson Counter, Sequential Circuit.


Paper Submission Last Date
30 - November - 2023

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