This is the matter-of-fact that communication system is never free from noise. Therefore it is a requirement for every communication systems to have suitable means to recognize and correct the errors in the information which is received over communication channels. Digital parallel FIR(Finite Impulse Response) filters are very widely used in DSP application. To get the noise free system, there is a need to implement some techniques to achievethe fault tolerancein parallel filters. In this paper , the idea of implementing FIR Filter with the range of 1 bit to 6-bit Fault tolerance using BCH codes is addressed.This idea is very much effective infault tolerance as well as comparatively less cost. Both features are evaluated for FPGA implementation.

Keywords : Error Correcting Codes (ECC); Finite Impulse Response (FIR) filter; Very Large Scale Integration (VLSI);HDL; FPGA.