Authors :
Srinath Bheemaraju; Teja Sri Venkat Saidhar Movva; Priyadharshini S; Gayathri Nair, Engineer; Chandravardhana Kuluru
Volume/Issue :
Volume 9 - 2024, Issue 5 - May
Google Scholar :
https://tinyurl.com/482zhe94
Scribd :
https://tinyurl.com/4bm6hd57
DOI :
https://doi.org/10.38124/ijisrt/IJISRT24MAY458
Abstract :
Multicore systems have gained significant
importance in the Automotive industry due to data-
intensive applications, such as image processing, high-
speed process, and GPS application. It enables
manufacturers to build smaller chips, simplifying board
architecture and routing, reducing power consumption and
cost and increasing programmability. Multicore platforms
are segregated into two categories namely Homogeneous
(symmetric) and Heterogeneous (asymmetric) multicore
systems.
In Homogeneous systems, all cores are the same,
including frequencies, cache sizes and functions. In
Heterogeneous systems, different cores operate with
different frequencies, cache sizes and functions.
In this paper, we are going to discuss various aspects
of homogeneous and heterogeneous multicore architectures
like number and level of caches, interconnection of the
cores, Physical and Temporal isolation, Energy Efficiency,
Concurrency, Performance, Reliability and Robustness
along with the evaluation of these two architectures for
applications based on the above-mentioned aspects.
Keywords :
Multicore System, ADAS, Automotive, Homogeneous, Heterogeneous, System on Chip, Communication, Interconnect bus, CoreConnect, AMBA, Wishbone, OS scheduling, Energy efficiency, Performance, Isolation, Temporal, Physical, Concurrency.
References :
- A.S. Radhamani, "Performance Analysis of Homogeneous and Heterogeneous Multicore Processor Using Static and Dynamic Schedulers," Asian Journal of Information Technology
- C. Leech and T. J. Kazmierski, "Energy Efficient Multicore Processing," Electronics
- Sergio Saponara and Luca Fanucci, Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time
- IntervalZero, "How to Optimize the Scalability & Performance of a Multicore Operating System," IntervalZero.com
- Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout. Reliability-Aware Scheduling on Heterogeneous Multicore Processors
- M. Mitić and M. Stojčev, "A Survey of Three System-on-Chip Buses: AMBA, CoreConnect and Wishbone," International Journal of Electrical and Computer Engineering
- J. Zamorano and J. A. de la Puente, "Memory Isolation in Many-Core Embedded Systems,"
- N. Aggarwal, P. Ranganathan, N. P. Jouppi, and J. E. Smith, "Configurable Isolation: Building High Availability Systems with Commodity Multicore Processors,"
- J. Cong and B. Yuan, "Energy-Efficient Scheduling on Heterogeneous Multicore Architectures,"
- A. Merkel and F. Bellosa, "Memory-aware Scheduling for Energy Efficiency on Multicore Processors."
- H. Omar, H. Dogan, B. Kahne, and O. Khan, "Multicore Resource Isolation for Deterministic, Resilient, and Secure Concurrent Execution of Safety-Critical Applications," IEEE Computer Architecture Letters, vol. 17, no.2, July Dec.2018
- R. Usselmann, "OpenCores SoC Bus Review," Rev. 1.0, January 9, 2001
- "Specification for the: WISHBONE System-on-Chip (SoC), Interconnection Architecture for Portable IP Cores," Revision: B.3, Released: September 7, 2002.
- "Wishbone B4, WISHBONE System-on-Chip (SoC) Interconnection, Architecture for Portable IP Cores,"
- Hwang-cheng Wang and Alagan Anpalagan, "Energy-efficient tasks scheduling algorithm for real-time multiprocessor embedded systems," Journal of Systems Architecture, vol. 57, no. 5, pp. 498-505, May 2011. doi: 10.1016/j.sysarc.2010.10.003.
- Nik Jedrzejewski, "Three Reasons Why Embedded Heterogeneous Systems Are More Efficient," NXP Blog, Jan. 30, 2019.
- ARM Cortex-A53 MPCore Processor Technical Reference Manual, Ver:r0P4,https://developer.arm.com/documentation/ddi0500/j/Introduction/About-the-Cortex-A53-processor.
- IJSRD - International Journal for Scientific Research and Development. (2014, May 24). A comparative Study of Different system-on-Chip Buses based on Industry standards: AMBA, CoreConnect and Wishbone.
- IJEERT - Kolte, Mahesh. (2014). Design and Verification Point-to-Point Architecture of Wishbone Bus for System On Chip.International Journal of Emerging Engineering Research and Technology. 2. 155-159.
- ARM, "AMBA,"https://developer.arm.com/ip-products/system-ip/amba.
- J. Yiu, "CHAPTER 6 - Cortex-M3 Implementation Overview," The Definitive Guide to the ARM Cortex-M3 (Second Edition), Newnes, 2010, pp. 99-108
Multicore systems have gained significant
importance in the Automotive industry due to data-
intensive applications, such as image processing, high-
speed process, and GPS application. It enables
manufacturers to build smaller chips, simplifying board
architecture and routing, reducing power consumption and
cost and increasing programmability. Multicore platforms
are segregated into two categories namely Homogeneous
(symmetric) and Heterogeneous (asymmetric) multicore
systems.
In Homogeneous systems, all cores are the same,
including frequencies, cache sizes and functions. In
Heterogeneous systems, different cores operate with
different frequencies, cache sizes and functions.
In this paper, we are going to discuss various aspects
of homogeneous and heterogeneous multicore architectures
like number and level of caches, interconnection of the
cores, Physical and Temporal isolation, Energy Efficiency,
Concurrency, Performance, Reliability and Robustness
along with the evaluation of these two architectures for
applications based on the above-mentioned aspects.
Keywords :
Multicore System, ADAS, Automotive, Homogeneous, Heterogeneous, System on Chip, Communication, Interconnect bus, CoreConnect, AMBA, Wishbone, OS scheduling, Energy efficiency, Performance, Isolation, Temporal, Physical, Concurrency.