Fpga implementation of aes key expansion algorithm in fully pipelined and loop unrolled architectures| International Journal of Innovative Science and Research Technology

FPGA Implementation of AES Key Expansion Algorithm in Fully Pipelined and Loop Unrolled Architectures

Authors : Kiran P V; Naveen Kumar Kanavi

Volume/Issue : Volume 5 - 2020, Issue 12 - December

Google Scholar : http://bitly.ws/9nMw

Abstract : This paper has an aim of comparing the implementation and performance of key expansion algorithm of Advanced Encryption Standard (AES) in fully pipelined and loop unrolled modes. Using Xilinx 14.1 ISE for simulation and synthesis, fully pipelined mode achieves a throughput of 51.65 Gbps. The loop unrolled mode achieves throughput of 20.84 Gbps and has very less device utilization and is suitable for implementation on low end FPGAs

Keywords : AES, Key Expansion, Fully Pipelined, Loop Unrolled, Throughput

This paper has an aim of comparing the implementation and performance of key expansion algorithm of Advanced Encryption Standard (AES) in fully pipelined and loop unrolled modes. Using Xilinx 14.1 ISE for simulation and synthesis, fully pipelined mode achieves a throughput of 51.65 Gbps. The loop unrolled mode achieves throughput of 20.84 Gbps and has very less device utilization and is suitable for implementation on low end FPGAs

Keywords : AES, Key Expansion, Fully Pipelined, Loop Unrolled, Throughput

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