Efficient Arithmetic Coder Design for SPIHT Image Compression

Authors : Rahila I. Mulla, Prof. Rupali R. Jagtap

Volume/Issue : Volume 2 - 2017, Issue 12 - December

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/o2tK9k

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

A memory-efficient arithmetic coder design using MATLAB and Verilog HDL for the set partitioning in hierarchical trees (SPIHT) image compression is illustratedin this paper. In this wavelet transform is performed on the image first then coefficients are processed in SPIHT compression module. Compressed bitstream obtained from SPIHT module is applied to Arithmetic coder module whose output is an encoded bitstream. Output is tested for bits/pixel efficiency and compared with other compression models. This design of SPIHT with AC gives very good compression coding rate bits/pixel. MATLAB and Modelsim are used for simulation.

Keywords : Arithmetic Coding, Coding Efficiency (Bits/Pixel), Set Partitioning in Hierarchical Trees (SPIHT), Verilog, Wavelet.


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