Detecting and Correcting Multiple Cell Upsets With 64-Bit Hamming Code in Memories


Authors : Nimita Sharma , Nidhish tiwari

Volume/Issue : Volume 1 - 2016, Issue 4 - July

Google Scholar : https://goo.gl/WGIfbL

The Transient MCUs (Multiple Cell Upsets) are becoming the big issues in memory reliability that exposed to environmental radiation. In order to prevent the MCUs are causing data-corruption. The more complex ECCs (error correction codes) is widely been used-to protect a memory; but the problem is which they required higher delay overhead. In order to gain the maximum capability of error detection; decimal algorithm is used by DMC. And again ERT (Encoder Reuse Technique) is given to extra circuit’s area overhead minimization without disturbing of entire encoding and decoding process. The DMC is used by DMC encoder to be a decoder part.In this paper , MCs (Matrix Codes) which based on HCs (Hamming Codes), have proposed for protection of memory. An important issue is that they’re DEC (double error correction) codes. And for MCU (32-bit), HC is capable of correction of 16-bits in single step. Here we worked on MCUs based on 32 and 64 bits. In 32 bits redundant bits are 23. And proposed HC (Hamming Code) is able to minimize LUTs and delay for 32-bits and 64-bits.

Keywords : ECCs (error correction codes), MTTF (mean time to failure), memory, MCUs (multiple cells upsets), Decimal algorithm, etc.

CALL FOR PAPERS


Paper Submission Last Date
31 - May - 2022

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.
Subscribe
OR

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.
Subscribe