Design of Carry Select Adder for Image Processing


Authors : Sriram k, Diviya KP, Vinothkumar T, Jeyaprabhu k, Kathirvel P.

Volume/Issue : Volume 3 - 2018, Issue 3 - March

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/EVUaqe

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

Digital image processing is one of the extensively used techniques in real life application in the field of Very Large Scale Integration (VLSI). Digital image processing techniques help in manipulation of the digital images by using computer algorithms. The use of carry select adders in Image addition shows reduced propagation delay and fast addition. By modifying the basic design of CSLA will results in high accuracy and less power consumption for image processing applications. In this paper, different designs such as Normal CSLA, Modified CSLA and Conventional CSLA are done. On comparing these designs, the result analysis shows that Conventional CSLA is achieved with greater accuracy and less area, delay and power consumptions.

Keywords : CSLA, Adder, FPGA, Image Processing.

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