Design Efficient and Scalable Reversible Arithmetic Logic Unit for Fixed and Floating Point Data


Authors : Bhupendra Singh Ahirwar, Prof. Sher Singh, Prof. Suresh S. Gawande.

Volume/Issue : Volume 3 - 2018, Issue 3 - March

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/W7hEZG

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

The advancement and improved of computerized world, for example, PC portable workstation adding machine and numerous computational gadgets utilized CPU. The CPU is heart of any computational and practical model. The fundamental centre some portion of CPU is ALU. The ALU play out the number-crunching operation for the working of advanced gadget. In this dissertation we design a very efficient ALU structure for the processing of high speed data and pattern analysis in the reversible mode. To improve the memory utilization and heat emission reduces the instruction cycle for the processing of data.

Keywords : Arithmetic Logic Unit, Central Processing Unit, Ripple Carry Adder, Personal Digital Assistant.

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