Authors : Gagana T M; Dr. Kiran Bailey

Volume/Issue : Volume 9 - 2024, Issue 6 - June

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Google Scholar : https://tinyurl.com/mse4jsxd

Scribd : https://tinyurl.com/yt3ehbnh

DOI : https://doi.org/10.38124/ijisrt/IJISRT24JUN1650

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Abstract : This project introduces a Phase-Frequency Detector (PFD) that includes a dedicated circuit for removing the dead zone. This design utilizes Pass Transistor Logic (PTL) and Delay Cells (DCs) to effectively address this issue. Additionally, a Low-Pass Filter is integrated into the system and connected with charge pump, employing a technique that replaces resistors with transistors, thereby significantly reducing the overall circuit area. Furthermore, a Phase-Locked Loop (PLL) serves to eliminate the dead zone and significantly reduce the circuit's size. This project aims to advance circuit design methodologies by enhancing performance and minimizing area requirements.

Keywords : Phase Frequency Detector, Low-Pass Filter, Pass Transistor, Delay Cells, Charge Pump, Phase-Locked Loop

References :

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4. Shruti Suman1 , K. G. Sharma2 , P. K. Ghosh3, “Design of PLL Using Improved Performance Ring VCO”, IEEE, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016
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