Design and Implementation of Pipelined Floating Point Multiplier using Wallace Algorithm


Authors : Shilpa Ambiger, Sanjay Eligar.

Volume/Issue : Volume 3 - 2018, Issue 8 - August

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/buVhHj

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

A digital circuit in which the changes in the state of the memory elements are synchronized to a clock (single-phase) signal is known as Synchronous Network. The optimization of the network is an important factor to reduce the overall manufacturing cost and increase productivity. The network parameters such as speed, area, power could be optimized. Lower power consumption and lesser area are some of the very important factors to be consider in the fabrication of DSP systems as well as good performance systems. Multipliers have comprehensive importance in both digital signal processors and microprocessors. So design of such high speed multiplier is very essential. Optimizing the speed as well as area of any multiplier is a prime design issue. Many methods are available to speed up a multiplier. This work incorporates with floating point pipeline technique for improving multiplier’s performance.

Keywords : Wallace algorithm; floating point; multiplication; sparten 3; ISE 14.2; verilog.

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