Authors : A. Sai Navya; A. Shravan Kumar

Volume/Issue : Volume 11 - 2026, Issue 2 - February

Google Scholar : https://tinyurl.com/3tuepeey

Scribd : https://tinyurl.com/ucsnvrt9

DOI : https://doi.org/10.38124/ijisrt/26feb1374

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Abstract : Static Random-Access Memory (SRAM) plays a crucial role in digital systems, enabling high-speed data storage and retrieval, which is essential for efficient computational performance. Its inherent advantages—such as rapid access times, low latency, true random-access capability, and strong reliability—have established SRAM as the preferred memory choice in cache designs and real-time data processing applications. This project investigates the performance and stability of conventional 6-transistor (6T) SRAM cells implemented in deep sub-micron technology nodes, specifically comparing 65nm, 45nm, and 22nm CMOS technologies. The analysis highlights that SRAM cells designed at the 22nm node achieve notable reductions in power consumption and delay compared to larger technology nodes, aligning with findings reported in prominent journals such as IEEE Transactions on Very Large-Scale Integration (VLSI) Systems. These improvements underscore the benefits of aggressive scaling while maintaining operational stability and robustness against process variations. The results validate that careful design and sizing optimisations at advanced technology nodes can effectively balance performance and area constraints, making 6T SRAM cells viable for high-density cache memory applications in modern digital architectures.

Keywords : 6T SRAM, Power Consumption, Delay, 64×64 Memory Array, Pre-Decoder, Process Variations, 22nm CMOS Technology.

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