Computing Performance Enhancement of VLIW Architecture Using Instruction Level Parallelism


Authors : V. Venkata Nagendra Reddy; A. Sudhakar;Dr. P. Sivakumar

Volume/Issue : Volume 5 - 2020, Issue 9 - September

Google Scholar : http://bitly.ws/9nMw

Scribd : https://bit.ly/3ciHTA2

DOI : 10.38124/IJISRT20SEP241

Our paper proposes the new method of processor architecture called as VLIW for enhancing the performance of the architecture. VLIW is the complexity architecture because the enormous number of registers, slices, flip flops, counters, operand, ALUs, and MUXs used. The VLIW has the fife stages of pipelines for executing the architecture are (1) fetching the 128-bit instruction memory, (2) decode stage or it is also called as the operands reading stage because the total number of operands are implemented in this stage, (3) execution stage, here the operations with the parallel executions units which has the four operations, (4) memory stage is used for loading or for storing the data from/to the memory and (5) write back stage in this stage the outputs of all the stage is collected and write back into the register file for storing the output values. The whole process of implementation is implemented in the FPGA of the family of Spartan-6 XC6SLX-3CSG324 device. In this proposed architecture the performance of the architecture is increased by reducing the time taken to execute the CPU of Xst completion of the architecture

Keywords : VLIW Architecture; Vector Processing; Instruction Level Parallelism; FPGA and VHDL Implementation

CALL FOR PAPERS


Paper Submission Last Date
31 - March - 2024

Paper Review Notification
In 1-2 Days

Paper Publishing
In 2-3 Days

Video Explanation for Published paper

Never miss an update from Papermashup

Get notified about the latest tutorials and downloads.

Subscribe by Email

Get alerts directly into your inbox after each post and stay updated.
Subscribe
OR

Subscribe by RSS

Add our RSS to your feedreader to get regular updates from us.
Subscribe