Altera FPGA’S for Assessment of Low Power and Energy Consumption


Authors : K. Baby Sai Srija

Volume/Issue : Volume 4 - 2019, Issue 7 - July

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://bit.ly/2Z2LSZb

Designing of low power was a main issue in manufacturing the mobile systems including its performance. Mobile electronics having high features usually have difficult calculations and tough processing that lead to a short battery life, mainly when low energy design is not taken into consideration. To prevent overheating of components along with VLSI technology, thermal design requires low-power techniques. In this research, many low power designs for ASICs, processors and FPGAs are examined in which ASICs are more flexible for using techniques that are oriented towards less power consumption. Three different designs used a cutting edge FPGA device to compare and analyze consumption of power and energy, and matrix multiplication is to be done on the Altera platform.

Keywords : FPGA, NIOS, Matrix Multiplication, ASIC, Energy-Efficient.

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