A Frame of Multiplier using Compactor


Authors : S.L.Bharathi, N.Pritha, G.Srividhya, D.Padma Priya.

Volume/Issue : Volume 3 - 2018, Issue 3 - March

Google Scholar : https://goo.gl/DF9R4u

Scribd : https://goo.gl/qvsfej

Thomson Reuters ResearcherID : https://goo.gl/3bkzwv

In this paper, Multiplier is designed efficiently using compactor to make them suitable for diverse speed, low power and compact VLSI implementations. Mainly two conflicts absorbed in VLSI implementation are area and speed. Our proposed design contributes best tradeoff between area and speed. In this paper three steps involved namely generation, reduction and addition. Compactor structure considerably reduces the delay time of the overall system.

Keywords : Addition, Compactor, Generation, Multiplier.

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